The Triple-DAC employs a current steering architecture with differential current outputs. It uses 6 linear bits and 4 binary bits, all of which are generated from within the current source array. The circuit is a current output DAC designed to be loaded by either single or double terminated 75Ohm Lines.
- 28nm SMIC Poly Sion Process, 7 Metals Used
- 1.8V and 1.05V Supplies.
- Triple Channel VDAC which is easily configurable as single VDAC or as 6 channel VDAC due to flexible layout
- Sense comparator in each channel for load detection
- 6-bit Gain Control
- Single-Ended or Differential Output Range
- Full scale output currents of 13.3mA to 34mA
- Current Consumption:
- 120mA @ IFS=34mA
- 50mA @ IFS=13.5mA
- DNL< 1LSB Typ.; INL< 2LSB
- SFDR > 48dB at 300MS/s, Fout= 1MHz, Vo=1Vpp
- Stand-By and Power-Down Modes
- Total Die Area pre-shrink (with biasing circuitry): 0.29mm2
- The Triple-DAC segmentation results in an excellent
- static performance and reduced glitch energy at the
- output. This also ensures parasitics within the DAC
- are minimized. Furthermore, the distortion at the
- output is greatly reduced by using propriety latch
- The combination of static performance, reduced glitch
- energy, minimized parasitics and reduced distortion,
- results in outstanding dynamic performance over a
- wide range of conditions including frequencies close to
- the DAC Nyquist frequency.
- This 10-bit DAC features an excellent static performance
- that includes ±1LSB DNL and ±2LSB INL.
- The gain of the DAC is 6-bit controllable over a range
- from -8dB to 0dB. This is achieved with integrated bias
- current circuitry.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
- Composite Video
- RGB Video