The 1.8V 100MHz Oscillators library includes a programmable oscillator macro I/O cell.
▪ 100 MHz programmable oscillator
These libraries are offered at both 16nm and a 12nm shrink. They
are available in a staggered CUP wire bond implementation with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the DVDD/DVSS power cells necessary for ESD protection, the POC cell, and a rail splitter to isolate the oscillator in its own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
- 100 MHz Programmable Oscillator Features
- ▪ Programmable drive strength for wider frequency range – 1 MHz to 100 MHz using industry standard external crystals.
- ▪ Optimized for stability and minimum jitter
- ▪ Power-down mode
- ▪ Operates on core power only (VDD/VSS cells embedded)
- ▪ In a forced bypass mode, the XI port can be driven by an I/O-level (VDVDD) clock signal.
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)