1.6T Ultra Ethernet IP Solution with PHY, Controller and Verification IP

The Synopsys 1.6T Ultra Ethernet IP solution, consisting of 1.6T MAC and PCS multi-rate Ethernet controllers, silicon-proven 224G Ethernet PHY IP, and verification IP, is designed to meet the performance requirements of interconnects in the scale-out of AI Clusters compliant to the upcoming Ultra Ethernet Consortium specification. The solution is based on the evolving IEEE 802.3dj Ethernet standard with support of the Ultra Ethernet MAC and PHY layers for a GPU, NIC or scale-up Switch. The IP solution supports Interconnects at the rates of 400G, 800G and 1.6T.

By providing a complete IP solution, Synopsys delivers latency optimization and ensures that all the IP functions seamlessly together to lower integration risk. The high-bandwidth, excellent performance of the Ethernet IP solution is optimized for low power, small area and low latency.

The best-in-class IP solution has undergone thorough validation with various hardware platforms, PHYs, and Ethernet verification suites across a diverse range of processes and foundries. Leveraging Synopsys’ extensive PAM-4 design expertise and a proven track record in high-speed Ethernet controller designs, designers can accelerate time-to-market and achieve first pass silicon success for their advanced SoCs.

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