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1.2 GHz Fractional-N PLL (71104)
This is a dual supply voltage fractional and Spread Spectrum Clock (SSC) Phase Locked Loop (PLL). It generates an output clock which is determined by a 6-bit pre-divider, 10-bit main-divider, 3-bit scaler and Delta Sigma Modulator (DSM). The input clock bypass mode, glitch-free function and SSC capability are available.
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Block Diagram of the 1.2 GHz Fractional-N PLL (71104)
pll IP
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