The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins (en_rx, ten, t_cal<1:0, oen) to configure the state of the receiver.
The interface to the core logic in transmitter mode includes the signal pins (in_p and in_n) to transmit data and the control pins (en_tx, x2i) to configure the state of the transmitter.
There are other two internal pins (vref12 and iref_20u_tx, iref_20u_rx) to get voltage reference and current references. IOP and ION are complementary pins to connect to the bonding pads. LVDS transceiver cell may be used for half-duplex data transmission. In this case, input oen controls the direction of the transmission (en_tx=1, en_rx=1). When oen = 1, block operates in the receiver mode –the transmitter output is in high impedance state. When oen = 0, block operates in the transmitter mode. In this case, the transmitter drives its output current into the differential LVDS line, with the polarity corresponding to the bit value being transmitted. This LVDS driver provides a double current mode (x2i=1) for system designs that employ double termination (near-end and far-end) of the differential signaling lines. Control pins (en_tx and en_rx) enable or disable transmitter and receiver. When en_tx=0, en_rx=1, block operates in the receiver mode –the transmitter output is in high impedance state and transmitter is disable. When en_tx=1, en_rx=0, block operates in the transmitter mode, receiver is disable. Block also comprises internal termination resistor with adjustable value. Input bits t_cal<1:0> are used for adjusting the termination resistance. The design target is to compensate 100 ohm resistance deviation from 20% to 10%. In order to use an external termination, the internal resistor may be switched off by setting low input ten.
The block is designed on TSMC 180 nm CMOS technology.
- TSMC CMOS 180 nm
- 3.3 V power supply
- 1.2 Gbps (DDR MODE) switching rates (600 MHz)
- Half-duplex or full-duplex operation mode
- Conforms to TIA/EIA-644 LVDS standards without hysteresis
- Temperature range: -60 °C to + 100 °C
- Optimized for pad-limited layout design
- Supported foundries: TSMC, UMC, Global Foundries, SMIC
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Point-to-point data receiver
- Point-to-point data transmission
- Multidrop buses
- Clock distribution
- Backplane data receiver
- Backplane data transmission
- Cable data receiver
- Cable data transmission