晶心与您相约在RISC-V 峰会； 了解唯一通过ISO 26262标准并完全兼容的 RISC-V CPU以及最新多核 4 路乱序处理器和多核 1024 位向量处理器

Visit Andes’ Exhibition Hall Display in Booth D4 to View Live Demonstrations of its Leading-Edge CPU IP Technology

SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces its diamond sponsor participation in the RISC-V Summit, the premier annual event held from December 13 to 14, 2022 in San Jose McEnery Convention Center. The company will contribute three presentations and will also demonstrate its cutting-edge RISC-V CPU IP solutions at booth #D4.

Andes President and CTO, Dr. Charlie Su, will present a wide range of RISC-V applications and introduce Andes’ new product lines which benefits the industry in the keynote speech “Expanding the RISC-V Horizon and Beyond” on December 14 at 10:00 AM. John Min, Director of Solution Engineering, Andes Technology USA, will introduce multiple new processors optimized for new application areas in his presentation “Future is Sideways - Not Only Up and Right” on December 13 at 4:45 PM. Furthermore, Hubert Chung, FAE Manager of Andes Technology, will give a talk on “Andes AI solutions: AndesClarity and NN/Vector Libraries” on December 14 at 1:00 PM at Demo Theater.

In these informative speeches, the audience will get to learn the leading AndesCore™ RISC-V processor IP solutions. They include the recently announced N25F-SE, the industry’s first and only ISO 26262 fully-compliant RISC-V CPU; just announced AX65, a multicore 4-way out-of-order superscalar processor; the new AX45MPV, the leading-edge Linux multicore 1024-bit vector processor; and the new D23, the new-generation compact, versatile, secured core for IoT applications.

Andes will showcase the development boards with AndesCore ™embedded at our booth, including MPU development board from Renesas, AI development kit with camera module from Canaan, high-performance industrial-grade microcontrollers from HPMicro, Bluetooth development kit from Telink, IT9836 TDDI demo board from ITE and PC802SCB 5G small cell reference design from Picocom.

Besides presentations and live demo, Andes will join the RISC-V Member Day which kicks off the whole event on December 12. Andes CEO, Frankwell Lin, along with Andes President and CTO, Dr. Charlie Su will be interviewed during the Future Watch press conference and make a 25-minute talk about corporate updates and latest products. In addition, Andes is sponsoring the Onsite Attendee Reception in the main exhibition hall on December 13 at 5:10 PM. Join fellow attendees and enjoy refreshments at the end of the first RISC-V Summit day of presentations!

Please don’t forget to visit Andes booth #D4 and participate in the lucky draw to win an Andes Embedded Razor Gaming Headset! It’s a good opportunity for RISC-V enthusiasts to reserve one-on-one discussion with Andes experts to explore RISC-V solutions in further depth.

Details of Andes’ sessions during the RISC-V Summit are as follows:

Monday, December 12,

• 11:00 -11:25 AM: Future Watch (Press Conference)

Tuesday, December 13,

• 4:45-5:10 PM: Presentation “Future is Sideways - Not Only Up and Right” by John Min, Director of Solution Engineering
• 5:10-8:30 PM: Onsite Attendee Reception

Wednesday, December 14,

• 7:30 -8:45 AM: RISC-V Influencers Breakfast
• 10:00 -10:20 AM: Keynote “Expanding the RISC-V Horizon and Beyond” by Dr. Charlie Su, President and CTO
• 1:00-1:40 PM: Demo “AI Solution Including AndesClarity and NN/Vector Libraries” by Hubert Chung, FAE Manager

For more information, please visit the RISC-V Summit website.

About Andes Technology Corp.

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com.