Cadence打造针对台积电N5工艺技术的完整DDR5 / LPDDR5 IP解决方案

Multi-standard memory interface IP allows a wide range of memory devices targeting high-capacity, high-speed, low-power and low-cost applications

SAN JOSE, Calif., 07 Oct 2020 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the immediate availability of a complete, silicon-proven Cadence^® IP supporting the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process. The multi-standard IP includes Cadence PHY and controller Design IP and Verification IP (VIP) and supports a wide variety of applications including data center, storage, artificial intelligence/machine learning (AI/ML) and hyperscale computing. Customers using Cadence and TSMC technologies can design advanced-process chips that connect to multiple memory types more quickly and with low risk.

For more information on the Cadence IP for DDR, please visit www.cadence.com/go/ddrippr.

Cadence’s IP collaboration with TSMC is critical in today’s market landscape. For example, the union of DDR5 and LPDDR5 protocol solutions in the same memory interface IP offers a high-speed, scalable solution from large to small memory footprints. The goal of this Cadence IP is to make DDR5 and LPDDR5 implementation predictable and successful and to make it a flexible solution. The multi-standard DDR5/LPDDR5 IP solution allows users to use a single chip to support multiple memory types in different environments, enabling their chips to be used in different markets and products with different DRAM requirements.

“Designers of next-generation intelligent products require simple, efficient access to high-performance memory,” said Malcolm Humphrey, vice president and general manager of the core compute business for the Compute and Networking Business Unit at Micron. “Micron’s collaboration with Cadence and TSMC enables leading-edge memory interface IP on advanced technology nodes, empowering the ecosystem by bringing complete DDR5 and LPDDR5 DRAM memory solutions to the most advanced systems on chips.”

“We’re pleased to see the delivery of Cadence’s DDR5/LPDDR5 IP on the TSMC 5nm process technology, which is optimized for the latest emerging application areas,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “Through our continued collaboration with Cadence, we’re enabling mutual customers to design with these solutions, benefiting from the remarkable performance and power boost of our most advanced process technology and quickly launching their new product innovations to market.”

“As we continue to expand our collaboration with TSMC, our latest DDR5/LPDDR5 IP in TSMC’s 5nm process technology uniquely addresses the needs of next-generation data center, AI/ML and hyperscale applications,” said Sanjive Agarwala, corporate vice president, R&D in the IP Group at Cadence. “Cadence IP solutions help customers simplify the design process so they can successfully deliver innovative, intelligent semiconductor products in a timely manner.”

The DDR5/LPDDR5 IP supports the Cadence Intelligent System Design^™ strategy, which enables advanced-node system-on-chip (SoC) design excellence. The IP leverages technology from Cadence’s silicon-proven DDR and high-speed SerDes designs as well as comprehensive verification capabilities with Cadence VIP, providing designers with the utmost confidence when implementing SoCs.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.