Unlock the full performance of your SoC architecture with a last level cache
CAMPBELL, Calif. – June 7, 2018 – Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced the CodaCache standalone last level cache (LLC) for high-performance systems-on-chip (SoCs).
The Arteris IP CodaCache LLC is highly configurable and offers system-wide performance improvements and power savings while providing seamless integration into SoCs with Arm® AMBA® AXI interfaces. Key benefits include:
- Improves system performance by significantly reducing the amount of time that on-chip processors waste waiting for memory accesses to complete
- Reduces power consumption by dramatically reducing the number of power hungry memory accesses which must be communicated to off-chip DRAM
- Configurable size and organization at design and runtime to allow tuning to meet the requirements of a wide range of the most demanding applications
- Can be added to any AXI bus in a SoC design. It is a completely standalone product and does not require interconnect. Design teams can reduce congestion in the physical layout by using multiple dedicated CodaCache LLCs.
- Can be partitioned such that some or all of its RAM can be used as a Scratchpad, which is a temporary workspace for local storage of critical data like real time code, hashing tables, statistics, and counters. Configuring CodaCache LLC to include Scratchpad RAM can significantly improve the performance and determinism of real-time applications.
CodaCache LLC is ideally suited for “supercomputer-on-a-chip” applications, such as advanced driving assistance systems (ADAS), machine learning applications, server/data center processing, and networking. The CodaCache IP is a versatile standalone product, providing unique flexibility in configuring the cache based on desired size and performance, application requirements or layout constraints. CodaCache LLC is specifically designed to easily integrate into existing AXI-based systems, allowing performance and power consumption improvements without making large, difficult changes to the systems’ architecture.
“The Arteris IP CodaCache reduces memory bottlenecks and saves power by allowing system-on-chip to employ a highly configurable last-level cache rather than solely communicating with off-chip memory,” said Mike Demler, Senior Analyst at The Linley Group and Senior Editor for Microprocessor Report. “Designers will be attracted to the variety of use cases that CodaCache IP supports, including dedicated, shared, and distributed partitioning, as well as its use as on-chip scratchpad storage.”
“The Arteris IP CodaCache LLC continues our heritage of offering SoC architects and design teams the means to tailor and optimize state-of-the-art on-chip communications IP to their unique requirements,” said K. Charles Janac, President and CEO of Arteris IP. “With CodaCache LLC, we are providing a new way for SoC teams to differentiate their chips while significantly reducing time to market.”
The CodaCache standalone LLC is available now.
About Arteris IP
Arteris IP provides network-on-chip (NoC) interconnect IP to accelerate system-on-chip (SoC) semiconductor assembly for a wide range of applications from automobiles to mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye (Intel), Altera (Intel), and Texas Instruments. Arteris IP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, the CodaCache standalone last level cache, and optional Resilience Package (ISO 26262 functional safety) and PIANO automated timing closure capabilities. Customer results obtained by using the Arteris IP product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit www.arteris.com.