New Silicon IP
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add encryption, compression ... in your datas
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create easily your own PCIe NVMe SSD
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LDPC Encoder / Decoder
- Full hardware
 - performance/gatecount
 - configurable generator matrix
 
		 
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PCIe - PCI Express Controller
- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
 - Test Bench. (Environment Variable : Verilog)
 - Methodologies - based Test Bench : UVM
 
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Securyzr™ neo Core Platform - One core, multiple products
- Secure Boot
 - Firmware update in the field
 - Secure key storage
 
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DDR5 Registering Clock Driver (RCD) (DDR5RCD03)
- Compliance as per JEDEC's JESD82-513
 - In I3C mode, SCL Operating speed 12.5MHz as Maximum
 - DDR5 server speeds up to 6000MT/s
 
		 
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InCore Azurite Series: 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- 32-bit RISC-V core
 - 2-stage pipeline
 - Available in many versions
 
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DisplayPort 1.2a TX PHY targeting 28nm Artix-7
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Pulse Per Second (PPS) Clock to PPS core
		 
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DisplayPort 1.4 IP-core
- Compact RTL footprint
 - Easy-to-use
 - Simple API
 
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VPU R3.0 on Artix 7 100T
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VPU R1.0 on Artix 7 200T
		 
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