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12-bit, High Speed Current Steering DAC in TSMC (65nm, 40nm, 28nm, 16nm, 12nm)
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VC Verification IP for CPRI
Synopsys® VC Verification IP for CPRI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CPRI based designs.
Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
Features
- CPRI specification 7.0
- Single agent, can be configured as RE or REC
- Multiple ports, with master or slave characteristics
- Interface: Serial as well as parallel (encoding bypassed)
- Automated error injection
- Configurable pattern generation for random, directed and error patterns
- SAP for user, control & management, and synchronization plane data
- IQ data configurable for payload, sampling width and AxC data mapping method
- Both C&M channels: Ethernet (Fast), HDLC (Slow)
- Passive link (no C&M channel proposed)
- Configurable line bit rate (614.4 Mbit/s—24330.24 Mbit/s) and automated link rate negotiation
- 8b/10b and 64b/66b encoding
- L1 in-band protocol—alarms and status
- Enable/disable scrambling
- FER
Benefits
- Native SystemVerilog/UVM
- Source code test suite (Optional)
- Built-in protocol checks
- Verification plan and coverage
- Extensive error injection
- Runs on all major simulators
Block Diagram of the VC Verification IP for CPRI Verification IP
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