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Simulation VIP for UCIE
Best-in-class UCIe Verification IP for your IP, SoC, and system-level design testing.
The Cadence® Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for UCIe runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify UCIe features at each functional layer (PHY, D2D, Protocol) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space. The VIP for UCIe can be used as a standalone or layered with PCIe and CXL VIPs.
Supported specifications: Universal Chiplet Interconnect Express Specification Version 1.0, February 2022, Errata for the UCIe Specification Rev. 0.7.
The Cadence® Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for UCIe runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify UCIe features at each functional layer (PHY, D2D, Protocol) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space. The VIP for UCIe can be used as a standalone or layered with PCIe and CXL VIPs.
Supported specifications: Universal Chiplet Interconnect Express Specification Version 1.0, February 2022, Errata for the UCIe Specification Rev. 0.7.
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Block Diagram of the Simulation VIP for UCIE
