Simulation VIP for JTAG

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.

Product Highlights
- Industry's first MR-IOV VIP
- Part of a complete PCI Express solution including: PCI Express Gen3, PCI Express Gen2, NVM Express, Mobile PCI Express, SR-IOV, MR-IOV
- Supports the latest specification ECNs

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