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ARINC 664 Verification IP
The ARINC 664 Verification IP is compliant with ARINC SPECIFICATION 664 PART 7 and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment.The SmartDV's ARINC 664 Verification IP is fully compliant with ARINC SPECIFICATION 664 PART 7 and provides the following features
ARINC 664 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
ARINC 664 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
ARINC 664 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
ARINC 664 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
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Block Diagram of the ARINC 664 Verification IP
