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WDT Verification IP

• The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
• The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.

GPIO Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for AMBA LTI

• LTI active and passive VIP supports both the specification version LTI-A and LTI-B

Simulation VIP for UCIE

• Support testbench language interfaces for SystemVerilog, UVM
• UVM building blocks

Universal Chiplet Interconnect Express (UCIe) Verification IP

• Supports Universal Chiplet Interconnect Express Specification Version 1.0, February 2022.

SPMI Verification IP

• Compliant with MIPI SPMI(1.0 and 2.0) specification.
• Supports multi-master and multi-slave model.

BoW Verification IP

• Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification

USB4 v2.0 Verification IP

• Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
• Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.

MASS Solution Verification IP

• Support full functionality of APHY as a physical layer
• Support Different PAL for multiple adaption layers for A-pkt conversion

UCIe Verification IP

• Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
• Unique development methodology to ensure highest levels of quality

TCP/TCPSW Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for MIPI SoundWire-I3S

• Support testbench language interfaces for SystemVerilog and UVM
• Generates constrained-random bus traffic with predefined error injection

GPIO Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

I2C Verification IP

AHB + APB VIP

• Comprehensive support for AMBA AHB
• Complex traffic sequence generators for normal and error scenarios

RoCE Verification IP

Synthesizable DDR to MIG Bridge

AMBA AHB Verification IP

Synthesizable LPDDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Simulation VIP for MIPI D-PHY, C-PHY and A-PHY

• Supports specification versions: 0.3.0
• Enables Transmitter and Receiver Design-Under-Test Configurations
• Provides Full Stack and Controller-only verification

VC Verification IP for DDR5

• August 2014 JEDEC LPDDR4 Standard
• 4Gb to 32Gb densities and x16 SRAM devices

MIPI CPHY Verification IP

• Supports MIPI CPHY Specification.
• Supports upt to 32 trio lanes.
• Supports to set symbol clock

Synthesizable DDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

UCIe Verification IP

• Support latest PCIe Gen5/6 and CXL 2.0/3.0
• Device and Retimer supported
• Multiple stacks / multiple protocol