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New Silicon IP
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Low Dropout (LDO) Capless Regulator
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PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm
- ± 4C temperature accuracy without trim
- ± 1C temperature accuracy after single room temperature trim
- Voltage monitor supports both single-ended and differential inputs, with 4:1 input mux
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40 mA LDO voltage regulator (3.3/5.0V to 1.8V)
- TSMC 180nm technology
- 1.8V output voltage
- Output voltage trimming
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Synopsys 224G Ethernet PHY IP for TSMC N3P
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PCIe - PCI Express Controller
- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
- Test Bench. (Environment Variable : Verilog)
- Methodologies - based Test Bench : UVM
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7.5 Gbps DDR CML IPs library
- TSMC 40nm LP process
- 2.5V IO voltage supply
- 1.1V core voltage supply
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PCIe 6.0 PHY IP for TSMC N5
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
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uLDO on TSMC 28nm
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uLDO on TSMC 130nm
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