10-Bit 64MHz 1.2V 1.9mW delta-sigma ADC, CMOS 130nm
AI accelerator (NPU) IP - 32 to 128 TOPS
Quad channel ADAS IP platform
CAT Trip Sensor, TSMC N4P
GUC 宣布成功推出业界首款采用台积电 3nm 和 CoWoS 技术的 UCIe 32G 芯片
Semidynamics 的 Aliado SDK 通过无缝集成 ONNX 加速 RISC-V 的人工智能开发
Arteris 发布新一代 Magillem Registers
Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Why RISC-V is a viable option for safety-critical applications
Rambus CryptoManager Root of Trust Solutions Tailor Security Capabilities to Specific Customer Needs with New Three-Tier Architecture
Arm Kleidi Arrives in Automotive Markets to Accelerate Performance for AI-based Applications
Dream Chip, Cadence Unveil Automotive SoC with Tensilica IP at embedded world '25
© 2024 Design And Reuse
版权所有
本网站的任何部分未经Design&Reuse许可, 不得复制,重发, 转载或以其他方式使用。
访问我们的合作伙伴页面了解更多信息
供应商免费录入产品信息