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XPS USB 2.0 Device
With this core, the Xilinx Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6.
This PLB slave interface supports single beat read and write data transfers (no burst transfers). This interface is suitable for USB-centric,high-performance designs, bridges and legacy port replacement operations.
This PLB slave interface supports single beat read and write data transfers (no burst transfers). This interface is suitable for USB-centric,high-performance designs, bridges and legacy port replacement operations.
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