32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Xilinx Virtual Cable
Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
This capability helps facilitate hardware debug for designs that:
* Have the FPGA in a hard-to-access location, where a "lab-PC" is not close by
* Do not have direct access to the FPGA pins – e.g. the JTAG pins are only accessible via a local processor interface
* Need to efficiently debug Xilinx FPGA or SoC systems deployed in the field to save on costly or impractical travel and and reduce the time it takes to debug a remotely located system
查看 Xilinx Virtual Cable 详细介绍:
- 查看 Xilinx Virtual Cable 完整数据手册
- 联系 Xilinx Virtual Cable 供应商
Interface and Interconnect IP
- Standard Compliant AMBA AXI SoC Interconnect, Soft IP
- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect