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XAUI PHY
The XAUI PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI applications. The XAUI PHY dwc_xaui3g_xN_pma_xN includes all the necessary logical, geometric, and physical design files to implement complete XAUI physical layer capability for 3.125-Gbps operation to connect a host or device controller to a XAUI system.
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