Implements the WiMAX IEEE802.16e/m specifications.
- Implements the WiMAX IEEE802.16e/m specifications.
- All 802.16 block sizes (40-4800) are supported.
- Based on our silicon proven high throughput LTE CTC decoder.
- Block-by-block change of block size / number of Iterations.
- Scalable decoder architecture, to support various throughput targets, from low to ultra high at constant number of iterations (400Mbps at 8 full iterations, technology dependent).
- Sophisticated early termination mechanism to support power saving and higher statistical throughput.
- All-synchronous design using a single clock, except for global asynchronous reset.
- Code optimizations for ASIC (power saving) and FPGA (area saving).
- Available as verilog (optional VHDL) source code.
- including the IEEE802.16m
- Verilog/VHDL source code or verilog EDIF netlist.
- Extensive Verilog testing environment.
- Bit-exact Matlab model.
- Detailed documentation.