Viterbi decoder for MIMO Wireless LAN 802.11n

特色

• K=7 (64 states) G0=171(octal), G1=133(octal).
• Rate ½. Other rates can be supplied by external puncturing.
• Parameterizable algorithm radix, 1/2/3 bits per clock.
• Throughput of 540 Mbit/sec can be reached in various combinations:
• A. 4 decoders of radix 1 at 135 MHz clock.
• B. 1/2 decoders of radix 2 at 270/135 MHz clock.
• C. 1 decoder of radix 3 at 180 MHz clock.
• Parameterizable input soft width.
• Parameterizable traceback length (memory depth).
• On the fly configurable traceback length, to support low latency.
• zero delay between packets.
• Memory type (SRAM / register file), supports Altera/Xilinx coding style for easy synthesis.
• Optional controls (decoder_en - for discontinuous data stream, decoder_abort - to reset the decoder).
• Supports low power features (clock gating, grey decoding, ...)
• Area/Power efficient architecture utilizing RAM for trace back storage (2 RAM instances)
• All-synchronous design using a single clock, except for global asynchronous reset.
• Available as verilog source code or as netlist.