MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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Virtex-6 FPGA GTX Transceiver Wizard
The LogiCORE™ Virtex®-6 GTXTransceiver Wizard automates the task of creating HDL wrappers to configure the on-chip GTX transceivers on Virtex-6 FPGAs. The Wizard’s customization GUI allows users to configure one or more GTX serial transceivers using either pre-defined templates supporting popular industry standards, or from scratch, to support a wide variety of custom protocols.
查看 Virtex-6 FPGA GTX Transceiver Wizard 详细介绍：
- 查看 Virtex-6 FPGA GTX Transceiver Wizard 完整数据手册
- 联系 Virtex-6 FPGA GTX Transceiver Wizard 供应商
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC