The Video LVDS SerDes Transmitter / Receiver IP Core provides a complete, easy-to-use Serializer/Deserializer (SerDes) solution to interface a wide variety of video host systems to Flat Panel displays.
The Video LVDS SerDes Transmitter / Receiver IP Core simplifies the design of video LVDS interfaces, improves data integrity and timing margins. For example, the Transmitter has the ability to generate a LVDS transmit clock synchronous to the video data stream thereby eliminating the need to fine-tune a PLL to the outputted LVDS data. Similarly, the Receiver auto aligns the receive clock to the encoded video to assure data synchronization. An easy to use GUI enables the user to select the number of LVDS links and to configure the number data channels for each link.
The Transmitter and Receiver cores support both 28 bit (8 bit RGB) and 35 bit (10-bit RGB) parallel data configurations using either 4 or 5 LVDS serial channels. Transmitter and Receiver modules can be cascaded to create dual and quad LVDS links supporting display panel resolutions up to 1080p at 120 Hz and beyond.