MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
You are here:
Video Decoder Interface
Video Decoder Interface core accepts BT601/656 video frames (digitized NTSC/PAL) in 10-bit Y'CbCr 4:2:2 format from a video decoder of an analog camera and outputs 16-bit video data in the same format in a continuous stream without blanking and synchronization information.
查看 Video Decoder Interface 详细介绍：
- 查看 Video Decoder Interface 完整数据手册
- 联系 Video Decoder Interface 供应商
Block Diagram of the Video Decoder Interface
FPGA IP Core IP
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet TSN Switch IP Core - Efficient and Massively Customizable
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes