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Video Codec
Innosilicon Video Codec is 4K multi-format codec IP supporting both H.265/HEVC and H.264/AVC video formats. This IP core provides high performance encoding and decoding capability up to 4K@60fps. Featuring a single-core architecture and optimized silicon area, the Innosilicon Video Codec IP is well-suited for 4k Ultra-HD applications such as security IP-cameras, wearable cameras, drone cameras, automotive, NVR and many others.
A single Video Processing Unit (VPU) can encode and/or decode any resolution up to 8192*4320. It guarantees real-time performance for encoding/decoding 4K 60fps based on its sophisticated, latency tolerant hardware architecture. To meet SoC customers’ needs, VPU is highly optimized for memory bandwidth loading and excellent power management.
VPU contains a 32-bit process called V-CPU, which is responsible for parsing bitstream syntax in decoder or encoding bitstream syntax in encoder from sequence to slice header unit, pre-scanning slice data, controlling the underlying video hardware blocks called V-CORE, and communicating with host CPU through host register interface. The V-CORE performs actual processing of coded slice data including entropy decoding, inverse scan, in-verse transform/quantization, motion compensation, and loop filtering, motion estimation, intra prediction, RDO, and entropy coding. This software and hardware combined architecture can provide flexibility and high throughput at the same time.
The Innosilicon Video Codec is easy to integrate into SoC with the support of the industry standard interfaces—32-bit AMBA3 APB bus for host CPU system control and 128-bit AMBA AXI for data transfer. There are six 128-bit AXI buses available—five for accessing external memory and one for on-chip SRAM memory.
A single Video Processing Unit (VPU) can encode and/or decode any resolution up to 8192*4320. It guarantees real-time performance for encoding/decoding 4K 60fps based on its sophisticated, latency tolerant hardware architecture. To meet SoC customers’ needs, VPU is highly optimized for memory bandwidth loading and excellent power management.
VPU contains a 32-bit process called V-CPU, which is responsible for parsing bitstream syntax in decoder or encoding bitstream syntax in encoder from sequence to slice header unit, pre-scanning slice data, controlling the underlying video hardware blocks called V-CORE, and communicating with host CPU through host register interface. The V-CORE performs actual processing of coded slice data including entropy decoding, inverse scan, in-verse transform/quantization, motion compensation, and loop filtering, motion estimation, intra prediction, RDO, and entropy coding. This software and hardware combined architecture can provide flexibility and high throughput at the same time.
The Innosilicon Video Codec is easy to integrate into SoC with the support of the industry standard interfaces—32-bit AMBA3 APB bus for host CPU system control and 128-bit AMBA AXI for data transfer. There are six 128-bit AXI buses available—five for accessing external memory and one for on-chip SRAM memory.
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