180nm OTP Non Volatile Memory for Standard CMOS Logic Process
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VESA DSC Decoder IP
DSC DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DSC DECODER IIP is proven in FPGA environment. The host interface of the DSC DECODER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
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vesa dsc IP
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- VESA DSC (Display Stream Compression) 1.2a Video Decoder
- VESA DSC Encoder
- VESA Display Stream Compression (DSC) IP Core
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs