VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs

特色

• Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
• Fully compliant with the DisplayPort 1.4a Standard
• Including the DSC slices per line requirements
• Supports up to 4 lanes at HBR3 rate (8.1 Gbits/sec)
• Configurable maximum display resolution up to 8K (FUHD) 60fps in RGB 444
• All color spaces supported by DSC v1.2a and component bit depth up to 12 bits
• Support for Xilinx® UltraScale™ and UltraScale+™ devices

Block Diagram of the VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs