This is a Very low gate count and zero latency run time data Randomize block.
It Randomize data in a way that it is not possible to make any meaningful content out of it.
The same engine can reverse the Obfuscation and convert the data back to original stream.
The Key of Obfuscation can be runtime programmable. so, one can manage different data for different streams.
Multiple memory regions can be defined each have separate key programmed.
Available for AHB and AXI Master and Slave interface.
- Features -
- 1. Data Obfuscation.
- 2. Minimum Latency of Zero Clock.
- 3. Multiple memory Regions with Separate Key.
- 4. AHB and AXI Master and Slave Interfaces supported
- 1. Runtime, High Throughput, Zero Latency.
- 2. Multiple memory Regions with Separate Configurable key.
- 3. SW Level Isolation. Only the right software can access right Data
- 4. Software and Master level Isolation of Data is possible with this block.
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
- If applied on Processor to create system wide Security Strategy. User can keep SW in Non User identifiable Mode and one cannot run the copied Firmware anywhere else.
- Can be applied of Secure Storage to Keep Data Secured from Hackers.
- Keys can be configured for each region separately can keep SW to Block their regions data to be used by anyone else.
- User can Apply on external memory Interface paths as well to secure data. There can be multiple usage based on chip designer point ov view.