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Very High Speed 3GPP LTE Turbo Decoder
This is a very high speed and fully compatible 3GPP LTE turbo decoder with one, two, four or eight parallel MAP decoders.
特色
- 8 state 3GPP LTE compatible turbo decoder
- Rate 1/3
- 40 to 6144 bit interleaver
- Up to 280 MHz internal clock
- Up to 204 Mbit/s with 5 decoder iterations
- 6-bit signed magnitude input data
- 1, 2, 4 or 8 parallel MAP decoders
- Optional log-MAP or max-log-MAP constituent decoder algorithms
- Up to 32 iterations in 1/2 iteration steps
- Optional power efficient early stopping
- Optional extrinsic information scaling and limiting
- Estimated channel error output
- Free simulation software
- Available VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.
可交付内容
- All Licenses
- Xilinx VHDL Core
- Test vector generation software
- VHDL ASIC License
- ASIC VHDL Core
- C++ bit/cycle exact simulation model
Block Diagram of the Very High Speed 3GPP LTE Turbo Decoder
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