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VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized
for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm Logic 1P8M Salicide
1.2V/3.3V process. This library is fully compliant with the JESD79F DDR SDRAM specification and
JESD79_2E DDR2 SDRAM specification.
for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm Logic 1P8M Salicide
1.2V/3.3V process. This library is fully compliant with the JESD79F DDR SDRAM specification and
JESD79_2E DDR2 SDRAM specification.
查看 VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library 详细介绍：
- 查看 VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library 完整数据手册
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SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library IP
- VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_01 I/O Cell Library
- SMIC 0.13um General Process, 1.2V/3.3V Standard I/O Library
- SMIC 0.13um 1.2V/3.3V PCI I/O Cells Library
- VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O 01C Library
- VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
- VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell