VDC-M Decoder IP

VDC-M DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. VDC-M DECODER IIP is proven in FPGA environment. The host interface of the VDC-M DECODER can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

• 查看 VDC-M Decoder IP 完整数据手册
• 联系 VDC-M Decoder IP 供应商