The present IP is a VCC Detector (VDT) circuit, which prevents the possibilities of causing Flash writing failure or internal operation failure by unstable supply voltage. It detects the voltage level of I/O (VIN). When the voltage is in the range of VTLL to VTLH, the output OUT_RD is generated as a high level. When the voltage is lower than VTLL or higher than VTLH, the output OUT_RD is generated as a low level.
This IP can’t stand-alone because it needs 0.5uA bias current and 1.0v reference voltage from external bandgap. The output may be in the wrong voltage level during the power-up phase before the bandgap becomes stable.