The present IP is a VCC Detector (VDT) circuit with normal operating voltage ranging from 1.08V ~1.32V. It first detects the core supply and then gives a control signal to level shift. Specifically, it detects the voltage level of input voltage VDD12. . When the detected supply voltage (VDD12) increases beyond the detection level (VR12), the corresponding output V12_RY is generated as a high level logic(V33); when the detected voltage(VDD12) decreases below the detection level(VF12), the corresponding output V12_RY is generated as a low level logic.