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USXGMII Subsystem
The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2.5G, 5G or 10GE over an IEEE 802.3 Clause 49 BASE-R physical coding sublayer/physical layer (PCS/PHY). The USXGMII IP core is delivered as encrypted register transfer level (RTL) through the Vivado® Design Suite targeted for Xilinx UltraScale+ and UltraScale devices.
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USXGMII Subsystem IP
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Quad core IP platform with integrated Arm security subsystem
- PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N3EP, TSMC 12FFCP, TSMC N4P, TSMC N5,
- PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N4P. N5 , N6
- Post-Quantum Security Subsystem (PQ-HW-SUB)