PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
USB3.2 PHY
Streamlined production testing is supported through BIST, multiple loopback modes and boundary scan. Its modular nature is flexible, ensuring a PHY combination that is able to support the latest in C-type connector configurations while including all the I/Os, ESD in a single drop-in block. As with all Innosilicon IP, our USB 3.2 solution is fully customizable to meet your specific needs.
查看 USB3.2 PHY 详细介绍:
- 查看 USB3.2 PHY 完整数据手册
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USB3.2 PHY IP
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
- USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
- USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 40LL