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USB3.1 PHY
With sophisticated architecture and advanced technology, KNiulink USB3.1 transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources. Data rate for Gen 1 physical layer is 5Gbps, and data rate for Gen 2 physical layer is 10Gbps.
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USB3.1 IP
- Combo SerDes PHY
- Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL
- Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process
- Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process
- Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process