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USB2.0 OTG IP
This IP is developed as the USB2.0 OTG PHY. This PHY consists of an analog PHY and a PCS layer. The PCS section includes basic encoding and decoding as well as data buffering, and the external interface is directly UTMI-compatible. Please note that full USB2 functionality requires the corresponding controller to work in conjunction. This PHY has been designed in HLMC28nm logic process CMOS technology.
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USB2.0 IP
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- USB2.0 Host Transceiver PHY
- USB2.0 OTG PHY supporting UTMI+ level 3 interface - 40LL / 110G / 130G / 130EF
- USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
- Embedded Host Controller 2.0