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USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
MSquare's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB 2.0 specifications from the USB Implementers Forum and delivers bandwidth up to 10Gbps. This high bandwidth capability is particularly beneficial for consumer and industrial video applications, as well as display, docking, cloud computing, and automotive applications.
As a leading supplier of USB IP, MSquare offers customers low-power, compact, and high-performance IPs featuring a unique hybrid analog/digital architecture. This IP supports all USB functions, including transceivers for 10G, 5G, 480M, 12M, and 1.5Mbps. It provides complete deliverables that simplify SoC integration and silicon validation. Available in a wide variety of process nodes from 40nm to 6/7nm, this IP features a compact die size and low pad count, enhancing product competitiveness in the USB market.
As a leading supplier of USB IP, MSquare offers customers low-power, compact, and high-performance IPs featuring a unique hybrid analog/digital architecture. This IP supports all USB functions, including transceivers for 10G, 5G, 480M, 12M, and 1.5Mbps. It provides complete deliverables that simplify SoC integration and silicon validation. Available in a wide variety of process nodes from 40nm to 6/7nm, this IP features a compact die size and low pad count, enhancing product competitiveness in the USB market.
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Block Diagram of the USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface

USB PHY IP
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P)
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP