This PHY IP supports both USB3.1 Gen1 & Gen2.This USB3.1 Gen2 PHY IP implements USB3.1 Gen2 transceiver and can be used as host and device. PHY IP supports USB3.1 Gen2 high speed data rate up to 10Gbps with integrated mixed signal circuit, also supports Gen1 5Gbps data rate. USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technology SMIC 14SF+/ SF++ process. The USB 3.1 PHY use a single efficient GDSII design that supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes. To maximize battery life in mobile applications, the USB 3.1 PHY is designed to minimize power consumption and standby current. This USB IP is the most certified USB IP solution in the industry. The USB 3.1 PHY IP is Silicon Proven and production proven including the digital controllers and vips in different applications.