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USB 3.0 SSIC PHY
The Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses the MIPI-M-PHY (Type-1) v. 3.0 to implement the SSIC adaptation to the USB3 PIPE interface. The USB 3.0 SSIC adapter is compliant with the “Inter-Chip supplement to the USB revision 3.0 specification, version 1.0” and the MIPI-M-PHY specification revision 3.0-r.03 and provides an effective data rate of up to 5.0 Gbps per lane, over 1 to 4 lanes of M-PHY. The USB 3.0 SSIC Bridge IP interfaces to the USB3 Device/Host controller with PIPE3 interface at 8/16/32-bit data width.
Leveraging the MIPI-M-PHY power management, SSIC adapter lowers the active power and idle power. The USB 3.0 SSIC adapter is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.
The USB 3.0 SSIC Adapter is delivered as digital RTL.
Leveraging the MIPI-M-PHY power management, SSIC adapter lowers the active power and idle power. The USB 3.0 SSIC adapter is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.
The USB 3.0 SSIC Adapter is delivered as digital RTL.
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Block Diagram of the USB 3.0 SSIC PHY
