Low jitter, low-power clock-deskew PLL operating from 6GHz to 9.5GHz on GF 22nm FDX
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USB 3.0 OTG PHY IP, UMC 55nm SP process
USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process.
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USB3 PHY IP
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 40LL
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 16FFC
- USB 3.0 PHY
- USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process