USB 2.0 picoPHY in TSMC (40nm, 28nm)

The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applications such as next—generation, feature-rich smartphones, netbooks, and mobile internet devices. For reduced silicon cost and longer battery life, the Synopsys USB 2.0 picoPHY IP delivers smaller die area and lower leakage power compared to current USB 2.0 PHY IP products. Optimized for mobile and consumer electronic applications, the Synopsys USB 2.0 picoPHY implements the latest Battery Charger version 1.1 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF). Architected for the industry’s most advanced process technologies, the USB 2.0 picoPHY is designed with features created to minimize effects due to variations in foundry process, device models, package and board parasitics. The Synopsys USB 2.0 picoPHY builds on years of customer success with Synopsys’ silicon-proven USB 2.0 PHY IP product line, which has been ported to over 50 process node and configuration combinations ranging from 180nm to 28nm. When combined with the Synopsys Host, Device or On-The-Go (OTG) digital controllers and verification IP, the Synopsys USB 2.0 picoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.

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