USB 2.0 picoPHY in TSMC (40nm, 28nm)

The Synopsys DesignWare® USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applications such as feature-rich smartphones and mobile internet devices. The DesignWare USB 2.0 picoPHY IP delivers 30% smaller die area and lower leakage compared to USB 2.0 nanoPHY IP products, for reduced silicon cost and longer battery life. Optimized for mobile and consumer electronic applications, the DesignWare USB 2.0 picoPHY supports the USB Type-C specification and implements the Battery Charger (version 1.1) and USB On-The-Go (OTG) version 2.0 specifications. Architected for the industry's most advanced 1.8V process technologies, the USB 2.0 picoPHY is designed to minimize effects due to variations in foundry process, device models, package and board parasitics.

The DesignWare USB 2.0 picoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 90-nm to 14/16-nm FinFET. When combined with the DesignWare digital controllers and verification IP, the DesignWare USB 2.0 picoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.

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