Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 – Small
USB 2.0 picoPHY in TSMC (40nm, 28nm)
The DesignWare USB 2.0 picoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 90-nm to 14/16-nm FinFET. When combined with the DesignWare digital controllers and verification IP, the DesignWare USB 2.0 picoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.
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Video Demo of the USB 2.0 picoPHY in TSMC (40nm, 28nm)
USB 2.0 has been around for over 20 years and is the world's most popular wired interconnect standard. Join Morten Christiansen and Gervais Fong as they discuss how the new eUSB2 standard enables USB 2.0 connectivity for SoCs in the most advanced process nodes.
USB PHY IP
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, 7nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- USB-C 3.1 SS/SSP PHY, Type-C in TSMC (16nm, 12nm, 7nm)
- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
- Complete USB Type-C Power Delivery PHY, RTL, and Software