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USB 2.0 PHY TSMC 40LP
The USB 2.0 PHY IP is a hard PHY macro for the TSMC 40LP process. Integrated I/O pads and ESD structures are available as an option.
The USB 2.0 PHY IP supports the USB 2.0 specification at speeds up to 480Mbps (HS). It is designed to easily integrate with a Cadence IP Factory USB controller, or any third party controller with a UTMI-compliant interface. It also supports the USB On-The-Go supplement to provide USB host and USB device operation.
This PHY IP is architected with CPF design flow and designed with low power considerations which make it a very mobile favorable design. It’s especially good for IoT applications, e.g. wearing devices, whom usually powered by little battery and the long battery life hours is a very much desired product feature. Thanks to a wide design tolerance considered in this design, though this PHY is implemented and verified at TSMC 40LP process, it also offer the flexibility to be easily migrated to other 55nm/65nm, e.g. TSMC 55LP/65LP, 55LPe/65LPe (embedded flash process).
The USB 2.0 PHY IP supports the USB 2.0 specification at speeds up to 480Mbps (HS). It is designed to easily integrate with a Cadence IP Factory USB controller, or any third party controller with a UTMI-compliant interface. It also supports the USB On-The-Go supplement to provide USB host and USB device operation.
This PHY IP is architected with CPF design flow and designed with low power considerations which make it a very mobile favorable design. It’s especially good for IoT applications, e.g. wearing devices, whom usually powered by little battery and the long battery life hours is a very much desired product feature. Thanks to a wide design tolerance considered in this design, though this PHY is implemented and verified at TSMC 40LP process, it also offer the flexibility to be easily migrated to other 55nm/65nm, e.g. TSMC 55LP/65LP, 55LPe/65LPe (embedded flash process).
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