USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
USB2.0 PHY IP transceiver 针对低功耗和最小die面积进行了优化,而不会牺牲性能和 high-data throughput. USB2.0 PHY IP 由一个具有Electrostatic Discharge (ESD) protection的完整on-chip physical transceiver 解决方案,被internal PLL提供的clock generation block,和一个resistor termination calibration circuit组成的确保给host 和device functionality完全支持。
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