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USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance. The USB2.0 IP implements a High-Speed USB 2.0 transceiver for use with either host and device function controllers. Compliant with the UTMI+ level 3 specification, the USB2.0 PHY IP integrates mixed-signal circuits to support High-Speed data rate at 480Mbps and is backward compatible to Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates. Targeting mobile and consumer product applications, the USB2.0 PHY IP also supports the supplementary USB Battery Charging specification.
The USB2.0 PHY IP transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high-data throughput. The USB2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, clock generation block provided by an internal PLL, and a resistor termination calibration circuit to ensure full support for host and device functionality.
The USB2.0 PHY IP transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high-data throughput. The USB2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, clock generation block provided by an internal PLL, and a resistor termination calibration circuit to ensure full support for host and device functionality.
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Block Diagram of the USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
