You are here:
USB 2.0 OTG PHY IP, UMC 65nm LP process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm LP/RVT Low-K Logic process.
查看 USB 2.0 OTG PHY IP, UMC 65nm LP process 详细介绍：
- 查看 USB 2.0 OTG PHY IP, UMC 65nm LP process 完整数据手册
- 联系 USB 2.0 OTG PHY IP, UMC 65nm LP process 供应商