MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
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USB 2.0 OTG PHY IP, UMC 0.18um eFlash/G2 process
USB2.0 OTG PHY, UMC 0.18um E-flash process.
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