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USB 2.0 Host Controller
The USB 2.0 Host Controller (USB20HC) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. The core supports High Speed (480 Mbit/s) mode, Full Speed (12 Mbit/s) mode and Low Speed (1.5 Mbits/s) mode operation.
The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. It is provided as Altera Quartus II Mega function (Altera SOPC Builder and Qsys ready component) and can be integrated easily into any SOPC Builder and Qsys generated system using Avalon bus.
The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. It is provided as Altera Quartus II Mega function (Altera SOPC Builder and Qsys ready component) and can be integrated easily into any SOPC Builder and Qsys generated system using Avalon bus.
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