USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)

The Synopsys IP USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and media players. Offering reduced silicon cost and longer battery life, the Synopsys IP USB 2.0 femtoPHY IP delivers 50% smaller die area and minimizes active and suspend power consumption. The Synopsys IP USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF) for dual role devices. Architected for the industry’s most advanced 1.8V process technologies, the USB 2.0 femtoPHY is designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitic. The Synopsys IP USB 2.0 femtoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 180- nm to 5-nm. When combined with the Synopsys Host, Device, and Dual Role digital controllers and verification IP, the Synopsys IP USB 2.0 femtoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.

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