You are here:
USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm)
The Synopsys DesignWare® USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and media players. Offering reduced silicon cost and longer battery life, the DesignWare USB 2.0 femtoPHY IP delivers 50% smaller die area and minimizes active and suspend power consumption.
The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF).
Architected for the industry’s most advanced 1.8V process technologies, the USB 2.0 femtoPHY is designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitics.
The DesignWare USB 2.0 femtoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 180-nm to 14-nm. When combined with the DesignWare Host, Device or On-The-Go (OTG) digital controllers and verification IP, the DesignWare USB 2.0 femtoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.
The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF).
Architected for the industry’s most advanced 1.8V process technologies, the USB 2.0 femtoPHY is designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitics.
The DesignWare USB 2.0 femtoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 180-nm to 14-nm. When combined with the DesignWare Host, Device or On-The-Go (OTG) digital controllers and verification IP, the DesignWare USB 2.0 femtoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.
特色
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications. Small PHY macro area: as small as 0.20 mm2. Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support.
- Supports most USB OTG 2.0 features, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). Battery charger v1.2 support including Accessory Charger Adapter (ACA) functionality.
- Enhanced test capabilities, including added CDR margin testing, automatic test packet generation, and reduced pin count test requirements via multiplexing of ID pin. Enhanced reference clock support for mobile and low-cost applications including 9.6, 10, 12, 19.2, 20, 24, and 50 MHz.
- Enhanced analog programmability and tuning for integration into low-cost packaging and PCB designs as well as external audio switch compensation. Reduced pin count with common ground design for lower packaging costs.
- Architecture designed to minimize effects due to foundry process, chip and board parasitics, and process device model variations. USB 2.0 Transceiver Macrocell Interface (UTMI + Level 3) specification (8-bit interface at 60 MHz and 16-bit interface at 30 MHz operation).
- On-chip PLL reduces clock noise and eliminates external clock generator requirement. Supports off-chip charge pump regulator for 5V Vbus. Designed for minimal power dissipation for low-power, self-powered, and bus-powered devices ©2018 Synopsys, Inc.
- All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at synopsys.com/copyright.html .
- All other names mentioned herein are trademarks or registered trademarks of their respective owners. 03/12/18.CS12523_dwc_usb2_femtophy. Suspend, resume, and remote wakeup mode support. USB 2.0 test mode support. Built-in self test features to confirm high-speed, full-speed and low-speed operation.
- Minimal external component cost; one external resistor. Low area ESD and CUP I/O pads provided with the macro. Enhanced design based on Synopsys’ industry leading USB implementer’s forum certified high-speed USB 2.0 nanoPHY and picoPHY architectures.
- Designed for rapid integration with Synopsys’ single-port high-speed USB 2.0 OTG, device and host controllers. Supports USB Type-C and traditional USB connectors.
优势
- Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
- Supports the USB 2.0 480 Mbps protocol and data rate (high-speed)
- Backwards compatible with USB 1.1 operating at 1.5 Mbps (low-speed) and 12 Mbps (full-speed) Integrates high-speed, mixed-signal custom CMOS circuitry designed to the UTMI+ Level 3 specification Can be used in USB device, host, or on-the-go applications
- USB-IF Certified
- Supports USB Type-C™ connector standard
应用
- Smartphones
- Tablets and ultrabooks
- Set-top boxes
- Smart TVs
- Media players
- Digital cameras and camcorders
- Wireless communication
- Gaming
- Storage
Video Demo of the USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm)
USB 2.0 has been around for over 20 years and is the world's most popular wired interconnect standard. Join Morten Christiansen and Gervais Fong as they discuss how the new eUSB2 standard enables USB 2.0 connectivity for SoCs in the most advanced process nodes.
查看 USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm) 详细介绍：
- 查看 USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm) 完整数据手册
- 联系 USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm) 供应商