The USB 2.0 Device with FIFO Interface (USB20HF) IP Core supports ULPI interface with Bulk IN and Bulk OUT endpoints. The core supports three preconfigured endpoints Control, Bulk IN, and Bulk OUT. It is Configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis1. Each configurable endpoint has an endpoint controller that supports Interrupt, Bulk, and Isochronous transfers. The USB 2.0 Device IP communicates with the Host through FIFO interface. The core supports both High Speed (480 Mbps) and full Speed (12 Mbps) functionality.
The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim pre-compiled library for core simulation and verification.