USB 2.0 Device Controller
Endpoints are controlled through a set of registers accessed through an AHB slave interface. Each of the up to 16 IN and 16 OUT endpoints can be individually configured to any of the four USB transfer types.
USB data cargo is moved to the core’s internal buffers using a master or a slave data interface. The data slave interface allows access directly to the internal buffers using AHB transactions and therefore does not need external memory. This makes it suitable for slow and simple functions. The data master interface requires an additional AHB master interface through which data is transferred autonomously using descriptor based DMA. This is suitable for functions requiring large bandwidth.
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USB IP
- HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- Multi-protocol SerDes PMA
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core